1. Field of the Invention
This application relates to methods of fabricating integrated circuit devices and, more particularly, to methods of fabricating memory cells for nonvolatile memory devices.
2. Description of Related Art
Nonvolatile memory devices are often used in electronic equipment due to their ability to store information in a memory cell even in the absence of power. One example of a nonvolatile memory device is an electrically erasable programmable read only memory (EEPROM) device. An example of an EEPROM device is a flash memory device.
Flash memory devices typically comprise a plurality of memory cells capable of storing electrical charge. The memory cells typically include a polycrystalline silicon (polysilicon) gate positioned over an insulating layer of silicon dioxide. The silicon dioxide layer is disposed over a semiconductor substrate, and the silicon dioxide layer may be referred to as a gate oxide layer or a tunnel oxide layer. The polysilicon gate positioned over the tunnel oxide layer may be called a floating gate. A second insulating layer is provided over the floating gate, and a second polysilicon gate is disposed over the second insulating layer. The second polysilicon gate may be called a control gate. Because the floating gate is electrically isolated between the two insulating layers, electrical charge stored on the floating gate is effectively trapped. The charges of the floating gates are controlled by the addition or removal of electrons from the floating gates. One process often used in changing the charges on the floating gates is Fowler-Nordheim tunneling, as is understood in the art.
Conventional methods for fabricating flash memory devices generally include first forming one or more bar-like structures on a semiconductor substrate having a tunnel oxide layer on one surface. The bar-like structures typically comprise a polysilicon layer and a dielectric structure disposed on the polysilicon layer. Thus, the polysilicon layer is disposed between the tunnel oxide layer and the dielectric structure. Subsequently, a second polysilicon layer and another insulative layer are disposed over the bar-like structures and the substrate to create a modified structure. The modified structure is then etched to create the isolated memory cells of the device. In other words, the isolated memory cells are created only after the addition of the second conductive layer and the insulative layer.
When these conventional methods are practiced, the resulting high aspect ratios (e.g., the depth to width ratios) and polysilicon stringers can become undesirable issues. For example, the individual memory cells are typically isolated by etching the modified structures and removing material between the cells. It is important to remove most, if not all, of the material on the tunnel oxide layer between the memory cells to permit the proper functioning of the memory device. As the height of the bar-like structures or memory cells increases, it becomes more difficult to remove material near the bottom of the memory cell (i.e., the area of the memory cell near the substrate). For example, when the memory cells are created after the addition of the second conductive layer and insulative later, as discussed above, it becomes difficult to completely isolate the memory cells. In one example, polysilicon stringers may remain after the etching processes. The stringers may provide contact between adjacent transistors, which may lead to electrical shorting paths between the transistors, and may induce problems in the functioning of the memory cells and the memory device.
In addition, because the etching rate of the anti-reflective coating (ARC) that is used in conventional methods is typically higher than that of silicon nitride (Si3N4) that may be used in the dielectric structure between the two polysilicon layers, the tunnel oxide and the semiconductor substrate may be damaged during etching for forming the memory cells.
Thus, there remains a need in the prior art for methods of fabricating memory cells that can address the conventional-methodology problems of, for example, reducing the difficulties in isolating high-aspect ratio memory cells and/or attenuating or eliminating stringers in the fabrication of those memory cells. In addition, a need remains in the prior art for memory-cell fabrication methods that can reduce or prevent damage to the tunnel oxide layer or the semiconductor substrate.
The present invention seeks to meet these needs by providing, among other things, methods of fabricating memory cells that isolate regions of the bar-like structures prior to the addition of the second conductive layer or control gate. Since the regions are isolated prior to the addition of the second conductive layer and insulating layer, the heights of the regions may be reduced compared to the heights of regions employing the above-discussed conventional methods. Consequently, more effective or complete isolation between the regions may be obtained. In addition, the occurrence of stringers should be attenuated or eliminated, since the ability to effectively etch the material between the regions is enhanced.
In one embodiment of the invention, a particular series of steps is provided that results in the selective etching of the various conductive layers and insulative layers, so that as a result the tunnel oxide layer and semiconductor substrate are minimally damaged, or not damaged at all.
The present invention provides methods for forming polyislands during, for example, the manufacture of nonvolatile memory devices, including flash memory devices. With particular reference to the disclosure herein, the term xe2x80x9cpolyislandsxe2x80x9d refers to isolated structures which are precursors to and which will eventually become integrated into memory cells. For example, polyislands may be formed into memory cells upon the addition of the second conductive layer (e.g., the control gate) and any additional insulative layers to the polyislands during manufacture of the memory cells. In accordance with one feature of the present invention, a polyisland may comprise a conductive layer and a dielectric layer disposed on the upper surface of the conductive layer. A plurality of polyislands are created by the parsing (e.g., etching of portions) of one or more polybars. As used herein, the term xe2x80x9cpolybarsxe2x80x9d refers to bar-like structures which are precursors to polyislands and which can comprise a conductive layer and a dielectric layer disposed on the conductive layer""s upper surface. Polybars can be formed, for example, using conventional etching procedures as understood by persons skilled in the art, and can be formed to extend generally from one side to the opposite side of the semiconductor substrate.
In accordance with one aspect of the present invention, an integrated circuit manufacturing method comprises a step of providing a semiconductor substrate having a substrate dielectric layer on a surface, followed by a step of forming at least one polybar on the substrate dielectric layer. Each polybar comprises a polybar conductive layer and a polybar dielectric layer, wherein the polybar conductive layer is disposed between the substrate dielectric layer and the polybar dielectric layer. The method may further comprise a step of patterning the at least one polybar to create a plurality of polyislands, before the addition of a second conductive layer to the semiconductor substrate.
A method for manufacturing a nonvolatile memory device in accordance with another aspect of the present invention comprises a step of providing a semiconductor substrate having a substrate dielectric layer disposed on one surface of the semiconductor substrate; another step of forming a first conductive layer on the substrate dielectric layer; another step of forming a second dielectric layer on the first conductive layer; and yet another step of patterning the second dielectric layer and first conductive layer to create at least one polybar having a length extending along the surface of the substrate dielectric layer. The method includes a further step of patterning the at least one polybar perpendicularly to the length of the polybar to thereby create at least one polyisland, followed by a step of forming a second conductive layer over the second dielectric layer of the at least one polyisland.
The foregoing methods may also comprise a step of disposing an anti-reflective coating over the at least one polybar. The methods may also be performed using a plurality of gas plasmas. Each of the gas plasmas may preferably have an etching selectivity for at least one of the anti-reflective coating, the second dielectric layer, or the first conductive layer. For example, the methods may comprise a step of etching the anti-reflective coating and the at least one polybar with a gas plasma having an approximately equal etching sensitivity to the anti-reflective coating and the polybar dielectric layer. The methods may also comprise a step of etching the anti-reflective coating and the polybar dielectric layer with a gas plasma having a greater etching sensitivity for the polybar dielectric layer compared to the anti-reflective coating. In addition, the methods may further comprise a step of etching the polybar conductive layer with a gas plasma having a greater sensitivity for the polybar conductive layer compared to the substrate dielectric layer.
In one embodiment of the invention, a method for forming polyislands comprises a series of steps including a step of providing a semiconductor substrate having a tunnel oxide layer disposed thereon; and another step of forming a plurality of polybars on the tunnel oxide layer. Each polybar includes a polysilicon layer and a silicon nitride (Si3N4) layer disposed on the polysilicon layer. An ARC layer is then formed on the semiconductor substrate over the polybars. Then, the polybars (and the ARC layer) are patterned perpendicularly to form a plurality of polyislands. The polybars are patterned using a three step etching process, which comprises the steps of: (a) etching with HBr/CF4 plasma as an etching gas plasma, wherein the etching selectivity between the ARC layer and the silicon nitride layer is approximately 1; (b) etching with CF4/CHF3/Ar plasma as an etching gas plasma, wherein the etching selectivity of the silicon nitride layer over the ARC layer is larger than 5; and (c) etching with HBr/He/Hexe2x80x94O2 plasma as an etching gas plasma, wherein the etching selectivity of the polysilicon over the tunnel oxide is greater than 50.
The foregoing methods may be practiced using, for example, high density plasma etchers and/or magnetically-enhanced reactive ion etchers. The foregoing methods may also include, for example, one or more steps of implanting dopants to the substrate and the conductive layers, such as the polysilicon layers. The methods may be used, for example, in fabricating flash memory devices.
Thus, by way of the present invention, polyislands can-be formed before the addition of a second conductive layer, or control gate. The control gates, or word lines, may then be formed on the polyislands. Since the polyislands are formed first, the relatively high aspect ratios and the stringer issues can be reduced or eliminated during the patterning of the word lines. In addition, the methods of the present invention can reduce or prevent damage to the tunnel oxide layer and/or semiconductor substrate during the etching processes.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art.
Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.